Thursday, 21 November 2013

Code for 2-Bit Adder in ModelSim SE 6.1 f

Q: Write Verilog code for two bit adder using two 1-bit adders. Also write its test bench and verify the results using simulations in Model Sim.

Answer:
module full_adder(sum, c_out, in1, in2, c_in);
            input in1, in2, c_in;  
            output c_out, sum;    
            wire w1, w2, w3;
            xor G1(w1, in1, in2);    
            and F1(w2, in1, in2);
            xor G2(sum, w1, c_in);
            and F2(w3, w1,c_in);
            or D1(c_out , w2, w3);
endmodule
module two_bit_adder(S0, S1, C2, A0, B0, A1, B1, C0);
            input A0, B0, A1, B1, C0;   
            output S0, S1, C2;    
            wire C1;
            full_adder A1(S0, C1, A0, B0, C0);    
            full_adder A2(S1, C2, A1, B1, C1);
endmodule
module testbench;
            reg A0, B0, A1, B1, C0;   
            wire S0, S1, C2;      
            two_bit_adder D1(S0, S1, C2, A0, B0, A1, B1, C0);
initial
begin
         A0=0; B0=0; A1=0; B1=0; C0=0;
#100  A0=0; B0=0; A1=0; B1=0; C0=1;    
#100  A0=0; B0=0; A1=0; B1=1; C0=0;             
#100  A0=0; B0=0; A1=0; B1=1; C0=1;
#100  A0=0; B0=0; A1=1; B1=0; C0=0;          
#100  A0=0; B0=0; A1=1; B1=0; C0=1;      
#100  A0=0; B0=0; A1=1; B1=1; C0=0;             
#100  A0=0; B0=0; A1=1; B1=1; C0=1;
#100  A0=0; B0=1; A1=0; B1=0; C0=0;          
#100  A0=0; B0=1; A1=0; B1=0; C0=1;     
#100  A0=0; B0=1; A1=0; B1=1; C0=0;              
#100  A0=0; B0=1; A1=0; B1=1; C0=1;
#100  A0=0; B0=1; A1=1; B1=0; C0=0;         
#100  A0=0; B0=1; A1=1; B1=0; C0=1;       
#100  A0=0; B0=1; A1=1; B1=1; C0=0;         
#100  A0=0; B0=1; A1=1; B1=1; C0=1;
#100  A0=1; B0=0; A1=0; B1=0; C0=0;        
#100  A0=1; B0=0; A1=0; B1=0; C0=1;       
#100  A0=1; B0=0; A1=0; B1=1; C0=0;             
#100  A0=1; B0=0; A1=0; B1=1; C0=1;
#100  A0=1; B0=0; A1=1; B1=0; C0=0;           
#100  A0=1; B0=0; A1=1; B1=0; C0=1;        
#100  A0=1; B0=0; A1=1; B1=1; C0=0;       
#100  A0=1; B0=0; A1=1; B1=1; C0=1;
#100  A0=1; B0=1; A1=0; B1=0; C0=0;          
#100  A0=1; B0=1; A1=0; B1=0; C0=1;        
#100  A0=1; B0=1; A1=0; B1=1; C0=0;        
#100  A0=1; B0=1; A1=0; B1=1; C0=1;
#100  A0=1; B0=1; A1=1; B1=0; C0=0;           
#100  A0=1; B0=1; A1=1; B1=0; C0=1;        
#100  A0=1; B0=1; A1=1; B1=1; C0=0;           
#100  A0=1; B0=1; A1=1; B1=1; C0=1;
end   
endmodule

Timing Diagram

Timing Diagram for 2-Bit Adder in ModelSim SE 6.1 f

Truth Table

Inputs
                                                                                      Outputs
A0
B0
A1
B1
C0
S0
S1
C2
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
0
0
0
1
0
0
0
1
0
1
1
1
0
0
0
1
1
0
0
0
1
0
0
1
1
1
1
0
1
0
1
0
0
0
1
0
0
0
1
0
0
1
0
1
0
0
1
0
1
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
0
1
1
0
0
1
1
0
1
0
0
1
0
1
1
1
0
1
0
1
0
1
1
1
1
0
1
1
1
0
0
0
0
1
0
0
1
0
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
0
0
1
1
0
0
1
1
0
1
0
0
1
1
0
1
0
1
0
1
0
0
1
1
0
1
1
0
1
0
1
1
0
1
1
1
0
1
1
1
1
0
0
0
0
1
0
1
1
0
0
1
1
1
0
1
1
0
1
0
0
0
1
1
1
0
1
1
1
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1

 Truth Table for two Bit-Adder